The present invention relates to fabricating semiconductor devices, and particularly to incorporating an embedded barrier layer in the interlevel dielectric layer of a replacement metal gate field effect transistor.
Field effect transistors (FETs) are commonly employed in electronic circuit applications. FETs may include a source region and a drain region spaced apart by a semiconductor channel region. In planar FETs, the semiconductor channel region may be a semiconductor substrate. In fin FETs, the semiconductor channel region may be a semiconductor fin. A gate, potentially including a gate dielectric layer, a work function metal layer, and a metal electrode, may be formed above the channel region. By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
Due in part to the relative instability of the dielectric layer and work function metal layer of the gate, a gate-last process, or replacement metal gate process, may be used where a sacrificial gate is formed prior to forming other components of the FET. The sacrificial gate may then be removed to form a recessed region that may then be filled with a replacement metal gate potentially including a gate dielectric layer, a work function metal layer, and a metal electrode. Because the replacement metal gate is formed after the other components of the FET, it is not subjected to various potentially damaging processing steps, for example high-temperature anneals.
After forming the FET, an interlevel dielectric (ILD) layer may be deposited above the FET to insulate the FET from surrounding structures. The ILD layer may be etched to form contact cavities, which may then be filled with metal to form contacts electrically connected to the source region, the drain region, and the gate.